This invention relates generally to an IC semiconductor memory device and more particularly to improvements relating to cell packing density while maintaining stable cell operation and small leakage current and lower on/off current ratio.
As new lithographic techniques are developed along with improvements in other semiconductor processing steps, it becomes continuously possible to reduce memory cell area. However, as is the case, as cell size is reduced, the properties of the cell are detrimentally affected so that new designs must be incorporated to achieve stable cell operation with good current ratio and small leakage current characteristics. In the case of memory cells incorporating load elements, such as in static random access memories (SRAM's) utilizing resistance loads in the form of a resistor or a thin film transistor, the operating characteristics of these elements is materially affected by reduced circuit scale integration to achieve more compact density.
FIGS. 1 and 2 show the conventional case for SRAM's having load elements comprising a resistance element. In FIG. 1, the semiconductor device comprises a substrate 101 on which is formed the conventional thin insulating film 103 for isolation. A conductive layer, forming an interconnect wiring 104, is formed over film 103 and insulating film 105 is formed over wiring 104 separating the latter from the structure above. A polycrystalline layer is then formed over insulating layer 105 and comprises low resistance regions 108 between which is high resistance (HR) region 109. Low resistance regions 108 are implanted with impurities, such as, phosphorus or boron, to render them highly conductive. On the other hand, HR region 109 contains a slight amount of impurities or no impurities at all. Lastly, a third insulating film is deposited over the polycrystalline silicon layer after which vias are formed to low resistance regions 108 to received the deposition of metal interconnect wiring 111, such as, aluminum.
HR region 109 is open to field effects created by voltage applications at wiring 104. These field effects directly affect the resistance value and pinch off characteristics of HR region 109 resulting in undesirable fluctuations and changes in the operating characteristics of the resistance element.
The conventional equivalent circuit structure of a memory cell utilized in a SRAM is shown in FIG. 2 wherein the load elements comprise high resistance polycrystalline silicon. As shown in FIG. 2, the polycrystalline silicon resistance load type memory cell comprises a flip-flop structure comprising a dual inverter, utilized for storing a value of information. One inverter is composed of driver MOSFET Q.sub.1 and a HR element R.sub.1 of polycrystalline silicon, and the other inverter is composed of driver MOSFET Q.sub.2 and a HR element R.sub.2 of polycrystalline silicon. An output of each inverter is connected as an input to the other inverter, i.e., as the gate input respectively to the driver MOSFETs Q.sub.1 and Q.sub.2.
The flip-flop structure is includes transfer MOSFETs Q.sub.3 and Q.sub.4 connected to the output of the inverters to receive from or transfer to a respective data line DL or DL a value of information. A power supply, V.sub.DD, is connected to one end of each of the HR elements R.sub.1 and R.sub.2, the other ends of which are connected to the drain regions of driver MOSFETs Q.sub.1 and Q.sub.2 and the source regions of transfer MOSFETs Q.sub.3 and Q.sub.4. The source regions of MOSFETs Q.sub.1 and Q.sub.2 are connected to ground (SL). Word line, WL, is connected to the gates of transfer MOSFETs Q.sub.3 and Q.sub.4 and the drain regions of these transistors are connected respectively to data lines DL and DL.
The memory cell of FIG. 2 is formed by means of forming MOSFETs Q.sub.1 -Q.sub.4 on semiconductor substrate wherein a first deposited conductive layer, such as, a polycide film, is utilized to form the gates for these transistors. Then, an insulating interlayer film is formed followed by the formation of an intrinsic polycrystalline silicon film which is formed over the surface of the insulating interlayer film. Then, regions of the intrinsic polycrystalline silicon film which will be utilized as HR regions are masked with a mask pattern layer and the exposed regions of this film are subjected to phosphorus diffusion or ion implantation of phosphorus atoms to render these regions of low resistance. Next, the mask pattern layer is removed and, then, the polycrystalline silicon film is patterned to assume the HR strip configuration and associated integral interconnect wiring wherein the strip configurations comprise intrinsic polycrystalline silicon HR regions R.sub.1 and R.sub.2 and integral low resistance regions, such as at 108 in FIG. 1. Problems are inherent in the foregoing described structure, particularly in the case where the integration scale of the memory cell is decreased, in that the consumption or leakage current, I.sub.DDS, i.e., the current flow from the power supply, V.sub.DD, to ground via R.sub.1 or R.sub.2 during standby when a respective driver transistor is driven into and remains in its ON state, is large and unacceptable. Typically, in the case of a 256K SRAM or a 1M SRAM, the leakage current, I.sub.DDS, is around 1 .mu.A with the potential drop between V.sub.DD and V.sub.SS of approximately 5 V.
To increase the length of HR regions R.sub.1 and R.sub.2, is not acceptable if the size of the cell is correspondingly increased. One way to reduce the leakage current would be to merely decrease the film thickness of the intrinsic polycrystalline silicon film. This would generally imply that the resistance values of resistance elements R.sub.1 and R.sub.2 would increase. However, the thinner the film thicknesses of the polycrystalline silicon film forming HR regions R.sub.1 and R.sub.2, the greater the influence in their operational affect due to the electric field effects imposed by adjacently disposed active elements, such as, MOSFETs Q.sub.1 and Q.sub.2, or an adjacent interconnect wiring, such as, wiring 104 in FIG. 1, or a biased semiconductive substrate either of which is set at a potential above ground. In the case of an underlying transistor comprising an interconnect layer serving as the source and drain region and another conductive layer formed to serve as a gate, the resistance values of HR regions R.sub.1 and R.sub.2 will vary depending upon the instantaneous state of operation of the transistor and corresponding effect of field ON or OFF conditions. Thus, it is difficult to manufacture these memory cells particularly according to either standard or new lithographic approaches imposing smaller integration scale with maintained stability of the resistance value design into HR regions R.sub.1 and R.sub.2 as well as with maintained low and stabilized leakage current, I.sub.DDS.
In the case of load elements comprising polycrystalline silicon transistors, it is difficult to reduce cell area toward smaller scale integration because a semiconductor memory, such as, a SRAM, utilize SRAM cells having a large cell ratio to maintain stable operation. To achieve this, the channel width of the driver MOSFET must be wider than that of the transfer MOSFET thereby directly effecting cell area reduction. FIG. 3 illustrates the conventional equivalent circuit for a memory cell of an SRAM utilizing polycrystalline silicon transistors as load elements in the cell. As shown in FIG. 3, the polycrystalline silicon transistor load type memory cell comprises a flip-flop structure comprising a dual inverter, utilized for storing a value of information. One inverter is composed of driver MOSFET Q.sub.1 and a polycrystalline silicon load TFT Q.sub.5, e.g., a polysilicon PMOS, and the other inverter is composed of driver MOSFET Q.sub.2 and a polycrystalline silicon load TFT Q.sub.6, e.g., a polysilicon PMOS. An output of each inverter is connected as an input to the other inverter, i.e., as the gate input respectively to the driver MOSFETs Q.sub.1 and Q.sub.2 and the gate input respectively to the load TFTs Q.sub.5 and Q.sub.6. The flip-flop structure includes transfer MOSFETs Q.sub.3 and Q.sub.4 connected to the output of the inverters to receive from or transfer to a respective data line DL or DL a value of information. A power supply, V.sub.cc, is connected to one end of each of the load TFTs Q.sub.5 and Q.sub.6, the other ends of which are connected to the drain regions of driver MOSFETs Q.sub.1 and Q.sub.2 and the source regions of transfer MOSFETs Q.sub.3 and Q.sub.4. The source regions of MOSFETs Q.sub.1 and Q.sub.2 are connected to ground. Word line, WL, is connected to the gates of transfer MOSFETs Q.sub.3 and Q.sub.4 and the drain regions of these transistors are connected respectively to data lines DL and DL.
In the case of the load TFTs Q.sub.5 and Q.sub.6, these devices include a thin polycrystalline silicon layer 200, illustrated in FIG. 4. Polycrystalline silicon layer 200 comprises a channel region 203 that is slightly doped with impurities or has no impurities, i.e., is intrinsic. Channel region 203 is integral to doped drain region 202 and doped source region 204. Polysilicon gate 206 is separated from channel region 203 by gate oxide layer 207. The structure of these TFTs include an off-set region 205 to prevent an increase of the offstate current as well as the drain current, I.sub.D, of the gate back voltage to achieve high on/off characteristics. However, owing to the influence of an approximate electric field from an active element, such as, driver MOSFETs Q.sub.1 and Q.sub.2, or from an interconnect wiring above or below load TFTs Q.sub.5 and Q.sub.6, such as interconnect wiring 208 in FIG. 4, or a biased semiconductive substrate, off-set region 205 is inverted by the field influence, as indicated by the marking "xxxxxx", and deterioration of the on/off characteristics occurs to load TFTs Q.sub.5 and Q.sub.6. Thus, it is important to eliminate the influence of such field effects, especially where smaller integration scale are to be utilized because the influence becomes more prominent as thickness layers are decreased to meet scale reduction rules and requirements.
It is an object of the present invention to provide a load element either of the polycrystalline silicon resistor type or of the polycrystalline silicon transistor type in memory cells of a semiconductor memory that provide a stabilized resistance value, low and stabilized leakage current, and a small on/off current ratio when utilizing smaller scale integration and, correspondingly, smaller cell size and cell ratio.
It is a further object of this invention to shield a load element of the polycrystalline silicon resistor type or of the polycrystalline silicon transistor type in memory cells of a semiconductor memory from the effects of a surrounding or adjacent electric field or other such fields that affect the stabilized operation and operating characteristics of the load element.